Bitstream radar waveforms for generic single-chip radar
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A Digital-to-Time converter (DTC) based on static CMOS multiplexers is presented, achieving a time resolution of 65 ps consuming 0.5 mW. The DTC relies on gate delay for programmability, ensuring robustness, linearity and wide delay range. Details of the transistor implementation (with sizes) is given, together with a detailed discussion on critical design points. Post layout simulations with Monte Carlo, voltage and temperature variations are presented with measurements from two different chip realizations in 90 nm CMOS.
Bjørndal, Øystein; Lande, Tor Sverre.
Power-efficient, gate-based Digital-to-Time converter in CMOS. Proceedings - IEEE International Symposium on Cicuits and Systems 2017